Spice Netlist
* Simulation of 2 Macthed Nmos Devices
I1 0 vgsn1 2µ
I2 0 vgsn2 2µ
Mn1 vgsn1 vgsn1 0 0 cmosn l=ln1 w=wn1 m=2
Mn2 vgsn2 vgsn2 0 0 cmosn l=ln1 w=wn1 m=2
*** ---------------------- Nominal "tt" nmos Corner Model ------------- ***
.MODEL CMOSN NMOS (LEVEL = 3
+VTO = 0.545
+KP = 2.06E-4
+ .... Rest of Model))
.end
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Statistical IC Design ; Modells How To
The first step toward Statistical Design is the ability to introduce mis-match into the simulation environment.
Consider the schematic, Spice netlist below.
I1 0 vgsn1 2µ
I2 0 vgsn2 2µ
*** Changed the nmos component in netlist with a subcircuit call. This makes the model inside the subckt unique. The added parameter in the netlist(mm) is used to control the model behavior. In this example mm can be used to skew one of the nmos devices.
*** Mn1 Matching skewed 1 sigma
XMn1 vgsn1 vgsn1 0 0 cmosn_mm l=ln1 w=wn1 m=2 mm=1
XMn2 vgsn2 vgsn2 0 0 cmosn_mm l=ln1 w=wn1 m=2 mm=0
*** -------------- nmos Mis-Match Model ----------------------------------------- ***
.SUBCKT cmosn_mm D G S BG
* Default Design Parameters
.params l=3.5e-7 w=4.0e-6 m=1
.param agNmos=1.0e6*sqrt(l*w*m)
.params mm=0 vtnMatch=0.01 kpnMatch=0.01
Mn0 D G S BG CMOSN_stat W={w} L={l} M={m}
.MODEL CMOSN_stat NMOS (LEVEL = 3
+VTO = {0.545+(mm*vtnMatch/agNmos)}
+KP = {2.06E-4*(1+(mm*kpnMatch/agNmos))}
+.... Rest of Model)
.ENDS cmosn_mm
.end
Since Mn1 and Mn2 call the same model from the same level of the hierarchy they can never be mis-matched. Now consider the revised netlist below.
Once the simulation models have configured to call the models as sub-circuits, statistical modeling can be implemented in the simulator environment. The exact implementation depends on the simulator and type of desired statistical analysis. The setup shown above is suitable for a RMS type system; mm=0 represents the nominal case, setting mm=1 on one of the devices yields a 1 sigma variation. The modified netlist above will produce a 1 sigma deviation in the mn1 device. Models for Monte Carlo Analysis varies slightly among the main Stream EDA tools.