ICDSN has experience developing statistical Simulation Models for Spectre, Hspice, and Smartspice. In cases when the wafer fab. supplies only corner models we build the model files and simulator setups for the customer... note that in most cases statistical design analysis can be implemented utilizing the standard analog EDA vendor tool setup.
- Statistical Simulation Modeling for Design Verification
Services
- VerilogA Model Development
VerilogA(AMS) is a powerful tool that ICDSN has used to reduce top level IC verification(simulation) time in SOC devices, automatically extract specification compliance matrix data, and emulate mixed signal systems behavior.
- Analog and Mixed Signal IC Development
ICDSN offers either fixed bid or hourly terms for IC development. Our EDA tools or your's. We do not maintain internal layout capability, but use several highly qualified contract layout vendors. If you have a foundry in mind we will work with them, if not we will help you pick one. We include characterization and will support ATE development. Most of our IC development programs have yield targets that must be achieved before ICDSN receives final payment.
- Post Design Design Problem Analysis, Yield Improment
ICDSN has extensive experience evaluating IC performance issues, generating root cause analysis, and correction actions. We can help you attain defect limited yields on analog centric IC's
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